An enhanced and improved multiplier circuit for a high speed application is proposed. In this paper, multiplier is designed using Braun array structure in dynamic logic. Here multiplication is implemented by using AND gate and the addition is implemented  by using ADDER. Multiplier is designed in dynamic logic so that overall delay gets reduced and this works faster compared to all other logic families. The simulation has been carried out in DSCH2 and microwind 2.6 tools using 0.12m CMOS technology. Parameters like speed, area, power are measured and finally, comparison is made between the results of parameters of multiplier designed using dynamic logic with the parameters of multiplier designed using CMOS logic. The circuit level technique can reduce the delay to 11pS and the speed increased to 0.36GHz.

multiplier, CMOS logic, dynamic logic, area, delay,  power dissipation.