The goal of image compression is to remove redundancy present in a data giving sufficient room for proper image reconstruction. There are numerous lossless and lossy compression techniques. Lossless compression techniques allow the image to be compressed by reducing the redundancy in the data where decompressed data is an exact copy of the original with no loss of data. However, lossy compression sacrifices the exact reproduction of the original image. JPEG is an example of lossy compression. One such compression is fractal image compression (FIC). FIC is a lossy compression technique and is also used for medical image compression. In this paper, a novel architecture for FIC is proposed, modeled and implemented on FPGA platform. The input image is grouped into  blocks, and simultaneously eight blocks are processed using parallel architecture. The nine isometries are realized using interleaver technique and a search/comparison operation is carried out using parallel architecture. The two parallel architectures have internal pipelined structure for arithmetic operations. The FSM control unit designed synchronizes the data movement and ensures codebook generation for  input data. The design operates at maximum frequency of 139.9MHz consuming less than 30% of FPGA resources consuming 0.46W of power. The design is suitable for real time medical image compression.

parallel architecture, internal pipelined structure, low power, interleaver structure, multiplexer logic.