As the size of the transistor keeps on decreasing with time, it becomes possible to place more and more logic on a silicon die. The logic becomes so complex that around 70% of the design phase is spent on functional verification. Therefore, there is a need for a methodology that reduces time to market and can be reused for multiple IP cores. Universal verification methodology is a well structured methodology which can be used for building verification environments, making them reusable with little modifications. For this paper, we have built a verification environment for the master block in ethernet management interface using UVM.

functional verification, system verilog, UVM, MDC MDIO, ethernet management interface.