This paper proposes a new low power phase accumulator (PA) based on pipelining carry-look ahead adder (CLA) for direct digital frequency synthesizer (DDFS). The aim is to focus on 32-bit phase accumulator design methods optimizing the PA design for either high-speed, low power, or both. Therefore, the PA are implemented using four methods, the first without pipelining, the second with 4-bit component adders or registers, the third with 8-bit components and the fourth with 16-bit components.

By making comparison between the four methods, the performance of the 32-bit phase accumulator design with 8-bit CLA Adder is best choice. This is because of the number of 4-inputs LUTs used are 149 only, and the number of occupied Slices are 86, and the average Fan-out of Non-clock Nets are 2.45 only. These results verify lower power consumption among other design methods. In addition, higher clock frequency with 150.4MHz, which means wide range of output frequency.

The proposed 32-bit design block PA was implemented using Xilinx ISE 12.1 environment. Xilinx (Spartan 3E) is used to model the PA using VHDL language.

direct digital frequency synthesizer (DDFS), carry-look ahead adder (CLA), phase accumulator (PA).