This paper presents a CMOS low-dropout (LDO) regulation with a dynamic-biased gain stage. The dynamic-biased gain stage which has the dynamic adjustable output resistance, current and gain is designed as a second stage driving the power transistor. A LDO regulator with the proposed gain stage has been implemented in a 0.18mm standard CMOS process and occupies 0.11mm² chip area. The experimental results show that the proposed LDO regulator can be stable without any additional on-chip compensation capacitors or complex circuit. The LDO regulator provides a full load transient response of settling time less than 15ms with a 2.2mF load capacitor and the voltage variation is less than 40mV. Furthermore, the load regulation and line regulation are 321mV/mA and 1.8mV/V, respectively.

CMOS, frequency compensation, low-dropout (LDO) regulator, dynamic-biased gain stage.