A novel pipelined architecture implementation of least mean square (LMS) adaptive FIR filter based on distributed arithmetic (DA) algorithm is presented. In conventional DA, partial product of filter coefficients is precomputed and stored in look up tables (LUTs) and it is required that filter coefficients are recalculated before filtering which reduces the throughput rate and also it requires address generation logic to update the table for every new samples. The conventional LUTs are replaced by register bank consist of pipeline latches and adder, to update the content of DA table in parallel. The parallel DA table updating and concurrent implementation of filtering and coefficients update operation of proposed design, increased the throughput rate significantly. The conventional shift and accumulate for summing up the inner partial product is replaced by carry save accumulation (CSA) to reduce area complexity and sampling period as well as using fast bit clock for CSA compare to other operation reduces the power consumption. The proposed method of implementation involves register bank, half of the logical element with same number of multiplexers compared to the existing DA based design. The proposed pipelined architecture for adaptive filter is implemented in Altera Quatrus-II EP2S15F484C3 device. From the implementation results it is found that the proposed design achieved 70.64% increased in throughput, 73% reduction in logic element and 27% reduction power consumption in average for filter lengths n = 4,  8, 16 and 32 compare to conventional DA based adaptive filter design.

least mean square, distributed arithmetic, carry save accumulator, pipeline architecture, adaptive filter, look up table, shift accumulate, offset binary coding, field programmable gate array.