In memory architecture, the standard complementary metal oxide semiconductor (CMOS) AND and CMOS NOR static decoders lie in the critical path that affects the overall speed of the memory. The internal circuitry in decoder is responsible for the huge time-delay and more power. Three novel address decoder structures have been proposed to select a particular memory cell in the array. Three novel address decoder structures are presented for the 2 to 4 decoder: a 16-transistor address decoder requires less transistor count and better delay performance, designed using pseudo-nMOS logic. A 20-transistor address decoder minimizes switching power and leakage power, designed using transmission gate logic. A 20-transistor address decoder minimizes the circuit complexity with reduced logical effort and parasitic delay and energy consumption, designed with the help of pass-transistor logic. These three topologies are extended to 4 to 16 and 5 to 32 decoder structures. The proposed decoder structures exhibit full-swing output voltage levels and minimized transistor count compared to the standard CMOS decoders. The proposed circuits are designed and examined using PSpice and the model parameters of a 22-nm CMOS technology; exhibit a significant improvement in delay and power compared to CMOS counterparts.

static decoders, low-voltage low-power logic styles, energy optimization, performance comparison.