FFT and IFFT are the key units in OFDM and in software defined radio. By optimizing those frequency transformation units, various performances like area and power can be optimized. To improve the performances of FFT, specific importance is given while developing a pipelined/parallel architecture for FFT and a better architecture has to be selected for twiddle factor multiplication unit. Bit parallel multiplier along with serial-parallel multiplier architecture provides better area requirement while comparing other multiplier units during implementation in VLSI hardware. A new algorithm is developed for multiplication of twiddle factor structure called “modified bit parallel multiplication (MBPM)” which is shifters based parallel multiplier architecture to reduce the area and power requirement. From the observations, it is seen that the MBPM algorithm requires only half the FPGA area requirement compared to other existing designs for most of the twiddle factor values for a 128-point FFT. The MBPM based twiddle factor multiplication units use less number of sub-expression shift elements compared to shift-add method for a 128-point FFT and it is an efficient implementation for 73% of its twiddle factors.

fast Fourier transform, twiddle factors, twiddle factor multiplication unit, bit parallel multiplication, barrel shifter.