FPGA IMPLEMENTATION OF CONCATENATED LT AND LDPC CODER FOR DEEP SPACE APPLICATIONS
With the advent of the space age, deep space exploration has increasingly become an important strategic task for human beings. Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. In this paper, we present a rateless coder which is the concatenation of Luby transform (LT) and low density parity check (LDPC) coders for space applications. The proposed coder is implemented using Xilinx ISE 90nm CMOS technology.
LT coder, LDPC coder, FPGA.
