An adder is an important module for cellular phones, mobile communication systems and digital signal processing applications. We present a modified 14 transistor adder architecture using a gate sharing technique and 20 transistor adder circuit based on bridge style technique. We prove that minimizing dynamic power consumption is achieved in both the structures. The enhancements are obtained by utilizing gate sharing and bridge style, technique at the transistor level. Spice simulations using CMOS technology that indicates proposed circuits gives better performance than the existing methods.

CMOS, low power, full adder, dynamic power.