This paper presents DFT (design for testability) feature insertion in a dual port RAM (random access memory) circuit. Power and area report of the design using VIVADO are also evaluated. The main focus is on designing the dual port RAM circuit for testability using scan testing (fast scan). Scan design is currently the most popular structured design for testability (DFT) method used in the industry. DFT patterns for the design were generated and > 99% test coverage and fault coverage were obtained. Multiple scan chains were inserted in the design in order to reduce clock cycles required to propagate data from input port to output port.