Multiply-accumulate unit is inevitable part of digital signal processors performing high speed operations like filtering, convolutions and so on. The optimization of the MAC is necessary not only for low power and high speed but also for the feasibility of the design in terms of real time applications. The present work focuses on both the aspects where various design architectures for individual blocks are optimized for low power using gating and high speed as well as the entire MAC is synchronized to perform the complete operation in single clock cycle utilizing pipelined structure to enhance the overall speed. The individual blocks take the data on the positive edges of the clock. The design is implemented using Cadence Virtuoso as well as Cadence NCSim in the 90nm technology. The two design approaches, analog and digital respectively, are compared to show the 6 times power reduction in analog design environment as compared to its digital counterpart.