Scaled technologies shrink the device parameters, increase the device density on the chip and further reduce the total chip area in digital logic implementation. In CMOS circuits, voltage scaling reduces the threshold voltage and device parameters, which increase leakage current in idle mode of the circuit, making it comparable with the dynamic power. The self-biasing transistor leakage reduction technique has been proposed to control static and dynamic power dissipation. We extend model analysis by studying the short-circuit power dissipation and effect of leakage power on supply voltage and temperature variations. In addition to that, the output voltage swing level of the proposed circuit can be modified by varying the size of the additional transistors and the capacitive load. The self-biasing design reduces the output voltage swing level up to 70% of the full swing level.