For the first time, the effect of every hundredth part of drain (and source) to substrate p-n junction length on OFF and ON current was studied. A numerical relationship between subthreshold leakage current and p-n junction length was proposed. A single NMOS bulk transistor of 20 nm technology generation was simulated by Sentaurus TCAD tool. Simulation result was found in close proximity to the theoretical proposal. Maximum 5613 times reduction in subthreshold leakage current was achieved. A tradeoff between leakage current reduction and ON current loss was also provided as a ready reference for designers to choose among various alternatives for designing low leakage or high speed transistor. As reduction of leakage current was done in device level, this methodology can be merged with any circuit level techniques.